User Manual
35 of 562
V 1.0
2021-08-25
XDPP1100 technical reference manual
Digital power controller
Voltage sense
Peripheral Field name
Access Address
Bits
Description
common
vsp2_cnt_vrsf2srr
R
7000_3068h [31:24] Non-averaged BVRSEN VRS comp
falling edge to SR FET rising edge
measurement result.
LSB = 5 ns, range = 0 to 1275 ns
common
vsp2_cnt_vrscomp_e
R
7000_306Ch [10:0]
Non-averaged BVRSEN VRS comp
pulse width measurement result for
ACF topology or the even half-cycle
of bridge topologies.
LSB = 5 ns, range = 0 to 1025 ns
common
vsp2_cnt_vrscomp_o
R
7000_306Ch [21:11] Non-averaged BVRSEN VRS comp
pulse width measurement result for
the odd half-cycle of bridge
topologies.
LSB = 5 ns, range = 0 to 1025 ns
common
vsp2_srr_b4_vrsf
R
7000_306Ch [22]
Status flag indicating BVRSEN
detected SR FET rising edge before
VRS comp falling edge (i.e., no dead
time on PWM falling edge) on
previous cycle.
0: SR FET rising edge after VRS
comp falling edge
1: SR FET rising edge before VRS
comp falling edge
common
vsp2_vrsr_b4_srf
R
7000_306Ch [23]
Status flag indicating BVRSEN
detected VRS comp rising edge
before SR FET falling edge (i.e., no
dead time on PWM rising edge) on
previous cycle.
0: VRS comp rising edge after SR
FET falling edge
1: VRS comp rising edge before SR
FET falling edge
telem
tlm_vin_src_sel
RW
7000_3400h
7000_3800h
[30:28] Input voltage telemetry source
select.
0: VRSEN, secondary V
RECT
sense,
vrs_voltage_init prior to start-up
1: BVSEN_BVRSEN, secondary V
RECT
sense, vrs_voltage_init prior to
start-up
2: Loop 0 V
OUT
, select on Loop 1
when Loop 1 V
IN
provided by Loop 0
V
OUT
(e.g., post-buck)
3: PRISEN, non-pulsed/primary V
IN
sense via telemetry ADC
4: tlm_vin_force, forced V
IN
via FW
(e.g., FW override of HW
computation)
5: VRSEN, secondary V
RECT
sense, 0 V
prior to start-up, select on Loop 1
