User Manual 536 of 562 V 1.0
2021-08-25
XDPP1100 technical reference manual
Digital power controller
Central processing unit subsystem
Register name Field name
Access Address
Bits
Description
CNTR
IFLG
W
700B_0008h [3]
Interrupt flag. IFLG is automatically
set to
“
1
”
when any of 28 (out of the
possible 29) I
2
C peripheral states is
entered (see STAT.CODE). The only
state that does not set IFLG is state
F8h. If the IEN bit is set, the interrupt
line goes high when IFLG is set to
“
1
”
.
If the peripheral is operating in slave
mode, data transfer is suspended
when IFLG is set and the low period
of the I
2
C bus clock line (SCL) is
stretched until
“
0
”
is written to IFLG.
The I
2
C clock line is then released
and the interrupt line goes low.
CNTR
STP
W
700B_0008h [4]
Master mode stop.
0: No effect
1: If set to
“
1
”
in master mode, a
STOP condition is transmitted on the
I
2
C bus. If STP is set to
“
1
”
in slave
mode, the peripheral will behave as
if a STOP condition has been
received but no STOP condition will
be transmitted on the bus. If both
STA and STP bits are set, the
peripheral will first transmit the
STOP condition (if in master mode)
then transmit the START condition.
The STP bit is cleared automatically.
CNTR
STA
W
700B_0008h [5]
Master mode start.
0: No effect
1: The I
2
C peripheral enters master
mode and will transmit a START
condition on the bus when the bus is
free. If the STA bit is set to
“
1
”
when
the peripheral is already in master
mode and one or more bytes have
been transmitted, then a repeated
START condition will be sent. If the
STA bit is set to
“
1
”
when the
peripheral is being accessed in slave
mode, the slave mode data transfer
will complete and master mode will
be entered when the bus is released.
The STA bit is automatically cleared
after a START condition has been
sent.
