User Manual
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V 1.0
2021-08-25
XDPP1100 technical reference manual
Digital power controller
Digital pulse width modulator
Figure 64
Fast-overshoot response waveform
The fast-overshoot response mode is enabled by setting the register
pid_ovs_entry_thrs
to any non-zero
value. While programming this register, it should be noted that:
•
At the system boot the FW reads and saves the setting of
pid_ovs_entry_thrs
and then sets it to 0.
•
On converter enable, the saved setting is restored to the register upon reaching the initial target voltage.
•
On converter disable it is reset again to 0.
The value does not need to be stored in OTP to be effective, and like most other registers changes while
regulating are permitted (e.g., to fine-tune response). The likelihood of triggering fast-transient response due to
the switching noise at the VSEN pin can be reduced in a similar way as discussed in the previous section by
using the LPF. The filter BW settings were summarized in
Refer to
Digital power controller XDPP1100
for additional information regarding
system tuning with respect to fast-overshoot response.
7.6
PWM interrupts
Both ramp generators (ramp0 and ramp1) are capable of setting two interrupts (IRQs). The following registers
define the interrupts triggered on timing markers t1 and t2:
•
rampX_t1_irq_sel
, for t1
•
rampX_t2_irq_sel
, for t2
The X denotes either 0 or 1. The programming of these registers is defined in
Table 46
Ramp generator interrupt programming
[2:0]
rampX_t1_irq_sel
rampX_t2_irq_sel
0
Disabled
Disabled
1
t1
t2
2
t1 even
t2 even
3
t1 odd
t2 odd
4 to 7
Set by rampX_irq_phase
V
RECT
falling edge
i
L
V
SEN
I
LOAD
ovs_slope_entry_thrs
ovs_exit_thrs
ovs_slope_exit_thrs
V
PRIMARY
ovs_entry_thrs
I
LOAD
T
SWITCH
