User Manual 520 of 562 V 1.0
2021-08-25
XDPP1100 technical reference manual
Digital power controller
Central processing unit subsystem
Register name Field name
Access Address
Bits
Description
ADDR_LUT7_A
DDR_CW
ADDR
RW
7008_005Ch [8:2]
Sets the slave address at which the
PMBus interface will respond.
ADDR_LUT7_A
DDR_CW
TYPE
RW
7008_005Ch [10:9]
Transaction type. Defines the type
of transaction associated with the
defined slave address.
0: PMBus transaction
1: I
2
C
2: Reserved
3: Reserved
DATA_LUT0_D
ATA_W
DATA
RW
7008_0080h [31:0]
The 32-bit data word 0 in 8x32-bit
(or 8x4-byte) scratch table used in
the prediction ACK/NACK approach
or as buffer for the data to be
transmitted over the PMBus
interface.
[31:24] = Byte 3
[23:16] = Byte 2
[15:8] = Byte 1
[7:0] = Byte 0
DATA_LUT1_D
ATA_W
DATA
RW
7008_0084h [31:0]
The 32-bit data word 1 in 8x32-bit
(or 8x4-byte) scratch table used in
the prediction ACK/NACK approach
or as buffer for the data to be
transmitted over the PMBus
interface.
[31:24] = Byte 3
[23:16] = Byte 2
[15:8] = Byte 1
[7:0] = Byte 0
DATA_LUT2_D
ATA_W
DATA
RW
7008_0088h [31:0]
The 32-bit data word 2 in 8x32-bit
(or 8x4-byte) scratch table used in
the prediction ACK/NACK approach
or as buffer for the data to be
transmitted over the PMBus
interface.
[31:24] = Byte 3
[23:16] = Byte 2
[15:8] = Byte 1
[7:0] = Byte 0
DATA_LUT3_D
ATA_W
DATA
RW
7008_008Ch [31:0]
The 32-bit data word 3 in 8x32-bit
(or 8x4-byte) scratch table used in
the prediction ACK/NACK approach
or as buffer for the data to be
transmitted over the PMBus
interface.
