User Manual
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V 1.0
2021-08-25
XDPP1100 technical reference manual
Digital power controller
Flux balance (FBAL)
o
Loop 0 is operating (start-up or regulation)
o
interleave operation enabled via PMBus command
PAGE0.FW_CONFIG_REGULATION.INTERLEAVE_ENABLE=1
If flux balance is not desired under the above conditions, the adjustment can be disabled by one of the
following two methods:
•
Setting
fbal_max
= 0 blocks the flux balance circuit from adjusting the PWM duty cycle (recommended
method)
•
Setting both PI filter coefficients to 0 in the OTP stored configuration sets the filter gain to 0, effectively
disabling the flux balance adjustment.
In addition to the above conditions, registers
rampX_dutyc_lock
must be set to 1 to enable even/odd duty-
cycle locking in the PWM. Note that the flux balance duty-cycle adjustment is applied after the duty-cycle lock
in the PWM function.
12.2
Flux balance PI filter
The voltage error is processed by the PI filter, which consists of:
•
A proportional term operating on the instantaneous volt-second or time error
•
An integral term operating on the accumulated volt-second or time error
The integral term sets the low-frequency gain and the proportional term sets the high-frequency gain of the
filter. The magnitude response of the filter is defined by Equations (12.1) to (12.4).
|𝐻
𝑃𝐼
(𝑓)| = √𝑘𝑝
2
+ (
𝑘𝑖
2𝜋∙𝑇𝑠∙𝑓
)
2
(12.1)
𝑘𝑝 = (8 + 𝑘𝑝_𝑓𝑏𝑎𝑙[2: 0]) ∙ 2
(𝑘𝑝_𝑓𝑏𝑎𝑙[5:3]−18)
(12.2)
𝑘𝑖 = (8 + 𝑘𝑖_𝑓𝑏𝑎𝑙[2: 0]) ∙ 2
(𝑘𝑖_𝑓𝑏𝑎𝑙[5:3]−22)
(12.3)
𝑇𝑠 =
1
𝐹
𝑠𝑤𝑖𝑡𝑐ℎ
(12.4)
Register values
kp_fbal
and
ki_fbal
larger than 55 are clamped to 55. Setting
kp_fbal
or
ki_fbal
to 0
individually disables the proportional or integral filter component. Note that when the integral component is
disabled through setting
ki_fbal
= 0, the accumulated current error is reset to 0.
magnitude response with the following values:
•
kp_fbal
= 48
•
ki_fbal
= 32
•
F
switch
= 250 kHz
