User Manual 488 of 562 V 1.0
2021-08-25
XDPP1100 technical reference manual
Digital power controller
Central processing unit subsystem
Register name Field name
Access Address
Bits
Description
detected (raw, prior to masking by
GPIOIE.INTENA), indicating that all
the requirements have been met,
before they are finally allowed to
trigger by GPIOIE. Bits read as zero
indicate that corresponding input
pins have not initiated an interrupt.
This register is read-only, and bits
are cleared by a reset.
For each bit [x]:
0: GPIOx interrupt conditions not
met prior to masking
1: GPIOx interrupt conditions met
prior to masking
GPIOMIS
INTMASK
R
6004_0418h
6005_0418h
[7:0]
The GPIOMIS register is the masked
interrupt status register. Bits read
high in GPIOMIS reflect the status of
input lines triggering an interrupt.
Bits read as low indicate that either
no interrupt has been generated, or
the interrupt is masked (disabled)
by GPIOIE.INTENA. This register is
read-only, and all bits are cleared
by a reset.
For each bit [x]:
0: GPIOx interrupt disabled or
conditions not met
1: GPIOx interrupt enabled and
conditions met
GPIOIC
INTCLR
W
6004_041Ch
6005_041Ch
[7:0]
The GPIOIC register is the interrupt
clear register. Writing a 1 to a bit in
this register clears the
corresponding interrupt edge
detection logic register. Writing a 0
has no effect. This register is write-
only and all bits are cleared by a
reset.
For each bit [x]:
0: GPIOx interrupt status
unchanged
1: GPIOx interrupt edge detect logic
cleared
GPIOAFSEL
MSEL
RW
6004_0420h
6005_0420h
[7:0]
The GPIOAFSEL register is the mode
control select register. Writing a 1
to any bit in this register selects the
hardware control for the
corresponding PrimeCell GPIO line.
