Infineon XDPP1100, Technical Reference Manual

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User Manual 374 of 562 V 1.0
2021-08-25
XDPP1100 technical reference manual
Digital power controller
Central processing unit subsystem
Register name Field name Access Address Bits Description
CLK_DEEP_SL
EEP_MSK_CNF
G_SET dse_bif_per_ssp_cl
k_g W 4000_2040h [14] Reserved
CLK_DEEP_SL
EEP_MSK_CNF
G_SET dse_bif_per_i2c_clk
_g W 4000_2040h [15] Enable bif_per_i2c_clk clock gating
when the Cortex®-M0 enters deep
sleep state.
0: Clock
“ bif_per_i2c_clk ” deep
sleep state clock gating status
unchanged
1: Enable clock
“ bif_per_i2c_clk ”
deep sleep state clock gating
CLK_DEEP_SL
EEP_MSK_CNF
G_SET dse_bif_per_uart_c
lk_g W 4000_2040h [16] Enable bif_per_uart_clk clock
gating when the Cortex®-M0 enters
deep sleep state.
0: Clock
“ bif_per_uart_clk ” deep
sleep state clock gating status
unchanged
1: Enable clock
“ bif_per_uart_clk ”
deep sleep state clock gating
CLK_DEEP_SL
EEP_MSK_CNF
G_SET dse_dtimer1_clk_g W 4000_2040h [17] Enable dtimer1_clk clock gating
when the Cortex®-M0 enters deep
sleep state.
0: Clock
“ dtimer1_clk ” deep sleep
state clock gating status
unchanged
1: Enable clock
“ dtimer1_clk ” deep
sleep state clock gating
CLK_DEEP_SL
EEP_MSK_CNF
G_SET dse_dtimer2_clk_g W 4000_2040h [18] Enable dtimer2_clk clock gating
when the Cortex®-M0 enters deep
sleep state.
0: Clock
“ dtimer2_clk ” deep sleep
state clock gating status
unchanged
1: Enable clock
“ dtimer2_clk ” deep
sleep state clock gating
CLK_DEEP_SL
EEP_MSK_CNF
G_SET dse_dtimer3_clk_g W 4000_2040h [19] Enable dtimer3_clk clock gating
when the Cortex®-M0 enters deep
sleep state.
0: Clock
“ dtimer3_clk ” deep sleep
state clock gating status
unchanged
1: Enable clock
“ dtimer3_clk ” deep
sleep state clock gating
CLK_DEEP_SL
EEP_MSK_CNF
G_SET dse_wdt_clk_g W 4000_2040h [20] Enable wdt_clk clock gating when
the Cortex®-M0 enters deep sleep
state.