User Manual 549 of 562 V 1.0
2021-08-25
XDPP1100 technical reference manual
Digital power controller
Central processing unit subsystem
Register name Field name
Access Address
Bits
Description
0: IrDA SIR ENDEC is disabled.
nSIROUT remains low (no light
pulse generated), and signal
transitions on SIRIN have no effect.
1: IrDA SIR ENDEC is enabled. Data
is transmitted and received on
nSIROUT and SIRIN. UARTTXD
remains high, in the marking state.
Signal transitions on UARTRXD or
modem status inputs have no
effect.
UARTCR
SIRLP
RW
700C_0030h [2]
SIR low-power IrDA mode. This bit
selects the IrDA encoding mode. If
this bit is cleared to 0, low-level bits
are transmitted as an active high
pulse with a width of 3/16 of the bit
period. If this bit is set to 1, low-
level bits are transmitted with a
pulse width that is three times the
period of the IrLPBaud16 input
signal, regardless of the selected bit
rate. Setting this bit uses less
power, but might reduce
transmission distances.
UARTCR
LBE
RW
700C_0030h [7]
Loopback enable. If this bit is set to
1 and the SIREN bit is set to 1 and
the SIRTEST bit in the test control
register, UARTTCR is set to 1, then
the nSIROUT path is inverted, and
fed through to the SIRIN path. The
SIRTEST bit in the test register must
be set to 1 to override the normal
half-duplex SIR operation. This
must be the requirement for
accessing the test registers during
normal operation, and SIRTEST
must be cleared to 0 when
loopback testing is finished. This
feature reduces the amount of
external coupling required during
system test.
If this bit is set to 1, and the
SIRTEST bit is set to 0, the UARTTXD
path is fed through to the UARTRXD
path.
In either SIR mode or UART mode,
when this bit is set, the modem
