Infineon XDPP1100, Technical Reference Manual

Page: 298 / 562

User Manual 298 of 562 V 1.0
2021-08-25
XDPP1100 technical reference manual
Digital power controller
Flux balance (FBAL)
12 Flux balance (F
BAL
)
This chapter discusses the flux balance feature as well as the relevant registers and their programming.
Flux imbalance is a known problem within isolated FB converters ( Figure 92 ). In these topologies timing
mismatch can cause the applied volt-seconds across the transformer during one half-cycle to be greater than
the volt-seconds during the opposite half-cycle. This might lead to transformer saturation due to flux
“walkaway”.
Typical solutions to avoid flux imbalance are:
•
Primary-side PCMC (requires current transformer)
•
VMC with capacitor in series with primary winding
•
VMC with oversized transformer or gapped transformer
Each method has drawbacks, adding either BOM cost or board area, or reducing efficiency. To overcome these
drawbacks while obtaining flux balance, the XDPP1100 contains two flux balance circuits to support interleaved
designs. It is capable of maintaining volt-second balance between half-cycles by using measured even/odd
half-cycle rectification voltages and pulse widths from the VS function as described in
section 2 .
Figure 92 FBCT system diagram
12.1 Flux balance circuit
A simplified block diagram of the flux balance circuit is shown in Figure 93 . The following signals are the inputs
to the flux balance circuit:
•
vrs_vrect_even and vrs_vrect_odd, which are the measured even and odd half-cycle rectification voltages
from the VS function
•
cnt_vrscomp_even and cnt_vrscomp_odd, which are the measured even and odd half-cycle rectification
voltage pulse widths from the VS function
Q
1
Q
2
S
1
S
2
+
V
OUT
-
L
OUT
C
OUT
Q
4
Q
3
V
IN
ISO
driver
Driver
Copper
XDPP1100
Turns ratio
n:1:1 V
RECT
V
R
EC
T
v
olt
ag
e
and t
im
e s
en
se
V
OUT
sense
I
OUT
sense
ISO
driver
VA
VB