User Manual
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V 1.0
2021-08-25
XDPP1100 technical reference manual
Digital power controller
Current balance (IBAL)
11
Current balance (I
BAL
)
This chapter describes the current balance functionality and the relevant registers and their programming.
Within interleaved topologies, different inductor currents may become imbalanced. This could be due to:
•
Component mismatches
•
Driver pulse width absorption
•
Transient timing with respect to the phase timing
The XDPP1100 supports interleaved topologies of a single loop with up to two phases driving a common output
voltage.
shows an example of an interleaved HBCT topology, where the inductor currents in L
OUT1
and
L
OUT2
may become imbalanced.
Figure 89
Interleaved HBCT system diagram
11.1
Current balance circuit
The XDPP1100 provides a HW-based current balance circuit. It aims to maintain equal currents on average in
the two phases of the interleaved converter by adjusting the duty cycle in one half of interleave. A simplified
block diagram of the current balance circuit is shown in
V
RECT1
V
RECT2
BV
RSEN
R5
R6
BV
RREF
V
OUT
C
OUT1
Ns
L
OUT1
V
RSEN
R3
R4
R1
R2
V
RREF
Ns
Np
V
SEN
V
REF
C
OUT2
Ns
L
OUT2
Ns
Np
T1
T2
V
IN
I
SEN
, I
REF
BI
SEN
, BI
REF
