User Manual 347 of 562 V 1.0
2021-08-25
XDPP1100 technical reference manual
Digital power controller
Central processing unit subsystem
Figure 101
Clock gating structure
15.3.2.3
Primary-source clock gating
The primary-source clock gating has the structure shown in
, where the last stage of gating is
controlled by the HOSC_SW_CLK_GATING_CTRL register or by the HOSC_HW_CLK_GATING_CTRL register while
the previous stages have a structure similar to the others.
The HOSC_HW_CLK_GATING_CTRL register enables the input signal CPUS_EN to take control of the CPUS
primary input clock source: a low-level CPUS_EN signal will gate the main clock, forcing the CPUS to enter the
hibernate state (if it has not already); a high-level CPUS_EN signal will remove the clock gate (HWEN_CLK=1),
recovering the previous CPUS functionality.
The HOSC_SW_CLK_GATING_CTRL register enables the SW to take control of the CPUS primary input clock
source. Gating the primary-source clock, the CPUS will freeze: external reset input signal assertion or WKUP_IN
signal assertion (if previously enabled by setting the proper bit in the SCU configuration register) has to be
provided. Asserting the external reset will force CPU to re-boot; while asserting the WKUP_IN signal the
processor code will continue to execute code from the last instruction.
CLK_IN
SLEEPDEEP
CLK_OUT
EN_CLK
Clock enable reg
Sleep mask
DeepSleep mask
G
Mux
GATEHCLK
&
0
0
0
&
0
0
0
