Infineon XDPP1100, Technical Reference Manual

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User Manual 114 of 562 V 1.0
2021-08-25
XDPP1100 technical reference manual
Digital power controller
Compensator
𝑉
𝑂𝑈𝑇,𝑡𝑎𝑟𝑔𝑒𝑡
=
𝑣
𝑐𝑜𝑛𝑡𝑟𝑜𝑙
𝑉𝑂𝑈𝑇_𝑆𝐶𝐴𝐿𝐸_𝐿𝑂𝑂𝑃
, (6.28)
Where:
•
V
control
is the internal reference voltage
•
VOUT_SCALE_LOOP is a PMBus command for external resistive divider
In the actual HW implementation, as shown in
Figure 51 , the scaling is obtained through register
pid_ff_one_div_vout_scale_loop . This parameter represents (1 / VOUT_SCALE_LOOP) and is automatically
computed by FW on initial configuration download and on any subsequent programming on
VOUT_SCALE_LOOP.
6.2.2 Input voltage source select and computation
The input voltage for the FF computation is selected through register pid_ff_vrect_sel from the following
sources:
•
VRSEN (V
RECT1
)
•
BVSEN_BVRSEN (V
RECT2
)
•
PRISEN (TS V
IN
)
•
Pid_ff_vrect_override
The rectified voltage V
RECT1
is the sensed voltage of the first loop at the VRSEN pin on the secondary side. In the
case of single-loop interleaved topology, the BVSEN_BVRSEN pin senses the phase two rectified voltage V
RECT2
.
These sensed voltages are obtained directly from the high-speed VSADC, which offers the best FF performance.
The TS PRISEN is one of the general-purpose ADC input channels, and it can be configured to sense the input
voltage on the primary side. PRISEN is obtained from the low-speed TSADC, and thereafter low-pass filtered in
telemetry. In this case, the FF performance is affected by the LPF BW, which can be programmed through
register
tlm_kfp_vin .
The FF computation can be overridden with FW, using the register
pid_ff_vrect_override . This option can be
used with:
•
General-purpose ADCs
•
Non-linear or non-positive slope LUTs
The V
RECT
override for FF computation uses the same data format as VRSEN/BVSEN_BVRSEN, as the
computation is performed in internal VSADC format.
Depending on whether the input voltage is sensed on the primary or secondary side, certain voltage scaling is
needed. The required scalings are defined as follows:
•
Secondary side: V
RECT
is sensed through an external resistor divider, and therefore the input sources VRSEN,
BVSEN_BVRSEN and pid_ff_vrect_override need to be scaled. The register tlm_vrect_scale_loop defines
the V
RECT
resistor divider and it can be configured through PMBus command MFR_VRECT_SCALE.
•
Primary side: The sensed input voltage needs to be scaled by the transformer turns ratio. This is performed
through register
pid_ff_i82_div_trans_scale_loop . This value is computed automatically by the FW based
on the PMBus command MFR_TRANSFORMER_SCALE.