User Manual
21 of 562
V 1.0
2021-08-25
XDPP1100 technical reference manual
Digital power controller
Voltage sense
It should be noted that the VCM output, V
control
, has higher resolution than the V
OUT
, thus resulting in an error
voltage with the resolution of 156.25 µV.
Programmable clamp (register
vsp_verrn_clamp_thresh
) is applied to limit the maximum error seen by the
compensation filter. A higher clamp threshold provides faster initial response to an abrupt change in the target
or output voltage, however, with the expense of increased overshoot or undershoot. A lower clamp threshold
provides moderate response to abrupt changes with less overshoot or undershoot. Because abrupt changes to
the target or output are not common under normal operating conditions, a low to medium clamp threshold
generally provides the best overall response.
2.3.2
Rectification voltage processing
For rectification voltage processing, the VS module is configured for V
RECT
via register
vsp1_vrs_sel
or
vsp2_vrs_sel
, depending on which input pins are used to sense the voltage. When V
RECT
is chosen, the VSP block
diagram of the processing function is shown in
. Compared to the V
OUT
, V
RECT
processing has many
more additional features.
Figure 10
Simplified block diagram of the rectified voltage processing
The V
RECT
VSP provides three outputs for further functions:
•
Measured V
RECT
of the even half-cycle (
vsp1_vsp_vrect_even
for VRSEN or
vsp2_vsp_vrect_even
for
BVRSEN)
•
Measured V
RECT
of the odd half-cycle (
vsp1_vsp_vrect_odd
for VRSEN or
vsp2_vsp_vrect_odd
for BVRSEN)
•
Average of the measured even and odd half-cycle V
RECT
(
vsp1_vsp_vrect
for VRSEN or
vsp2_vsp_vrect
for
BVRSEN)
The even and odd V
RECT
outputs are utilized by flux balancing in the case of FB topology. For other functions,
such as telemetry or faults, this separation is unnecessary, and they apply the average output. It should be
noted that non-bridge topologies do not have even/odd half-cycles and the output is sampled only on the
vsp_vrect_even
output and thus the average function only passes through even.
The state machine controls the ADC sample timing based on the detected edges of:
•
PWM
Decimator
50 MHz
100 MHz
vsadc
u12.0
Gain and
offset trim
State
machine
and
counters
pwm_even
vrs_comp
vsp_vrect_odd
vsp_vrect_even
vrs_track
vrs_hold
vsp_cnt_vrscomp_e,
vsp_vrscomp_o
vsp_cnt_srf2vrsr,
vsp_cnt_srf_avg
vsp_cnt_vrsf2srr,
vsp_cnt_srr_avg
vsp_vrect
1
0
vin_mode
pwm_odd
Average
D
Q
CLR
Q
SET
D
Q
RST_N
Q
Update
D
Q
RST_N
Q
Update
