NXP Semiconductors Kinetis KE1xZ256, Reference Manual

Page: 373 / 1325

• Can be used as a source for the LPFLL
• Can be selected as the clock source for the MCU system clocks
• Clock monitor with reset and interrupt request capability for SOSC, clocks
See the Clock Distribution Chapter for more information.
18.3 Memory Map/Register Definition
This section includes the memory map and register definition.
The SCG registers can only be written when in supervisor mode. Write accesses when in
user mode will result in a bus transfer error. Read accesses may be performed in both
supervisor and user mode.
NOTE
For any writeable SCG registers, only 32-bit writes are allowed.
8-bit or 16-bit writes will result in transfer errors.
SCG memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4006_4000 Version ID Register (SCG_VERID) 32 R 0100_0000h 18.3.1/374
4006_4004 Parameter Register (SCG_PARAM) 32 R See section 18.3.2/374
4006_4010 Clock Status Register (SCG_CSR) 32 R See section 18.3.3/375
4006_4014 Run Clock Control Register (SCG_RCCR) 32 R/W See section 18.3.4/377
4006_4018 VLPR Clock Control Register (SCG_VCCR) 32 R/W See section 18.3.5/379
4006_4020
SCG CLKOUT Configuration Register
(SCG_CLKOUTCNFG)
32 R/W 0300_0000h 18.3.6/381
4006_4100 System OSC Control Status Register (SCG_SOSCCSR) 32 R/W See section 18.3.7/382
4006_4104 System OSC Divide Register (SCG_SOSCDIV) 32 R/W 0000_0000h 18.3.8/384
4006_4108 System Oscillator Configuration Register (SCG_SOSCCFG) 32 R/W 0000_0010h 18.3.9/385
4006_4200 Slow IRC Control Status Register (SCG_SIRCCSR) 32 R/W 0100_0005h 18.3.10/387
4006_4204 Slow IRC Divide Register (SCG_SIRCDIV) 32 R/W 0000_0000h 18.3.11/388
4006_4208 Slow IRC Configuration Register (SCG_SIRCCFG) 32 R/W 0000_0001h 18.3.12/389
4006_4300 Fast IRC Control Status Register (SCG_FIRCCSR) 32 R/W See section 18.3.13/390
4006_4304 Fast IRC Divide Register (SCG_FIRCDIV) 32 R/W 0000_0000h 18.3.14/392
4006_4308 Fast IRC Configuration Register (SCG_FIRCCFG) 32 R/W 0000_0000h 18.3.15/393
4006_430C Fast IRC Trim Configuration Register (SCG_FIRCTCFG) 32 R/W 0000_0000h 18.3.16/394
4006_4318 Fast IRC Status Register (SCG_FIRCSTAT) 32 R See section 18.3.17/395
Table continues on the next page...
Chapter 18 System Clock Generator (SCG)
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
NXP Semiconductors 373