NXP Semiconductors Kinetis KE1xZ256, Reference Manual

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If the channel input does not have a filter enabled, then the input signal is always delayed
3 rising edges of the FTM input clock, that is, two rising edges to the synchronizer plus
one more rising edge to the edge detector. In other words, the CHF bit is set on the third
rising edge of the FTM input clock after a valid edge occurs on the channel input.
39.5.5.1 Filter for Input Capture mode
The filter function is only available on channels 0, 1, 2, and 3.
First, the input signal is synchronized by the FTM input clock. Following
synchronization, the input signal enters the filter block. See the following figure.
FTM input clock
filter counter Logic to define
the filter output
filter output
divided by 4
channel (n) input after
the synchronizer
Logic to control
the filter counter
CHnFVAL[3:0]
C
S
Q
CLK
Figure 39-13. Channel input filter
NOTE
The Channel Input Filter internal counter clock is further
divided by 4 in order to reject high frequency glitches.
When there is a state change in the input signal, the counter is reset and starts counting
up. As long as the new state is stable on the input, the counter continues to increment.
When the counter is equal to CHnFVAL[3:0], the state change of the input signal is
validated. It is then transmitted as a pulse edge to the edge detector.
If the opposite edge appears on the input signal before it can be validated, the counter is
reset. At the next input transition, the counter starts counting again. Any pulse that is
shorter than the minimum value selected by (CHnFVAL[3:0] × 4 system clock cycles) is
regarded as a glitch and is not passed on to the edge detector. A timing diagram of the
input filter is shown in the following figure.
The filter function is disabled when CHnFVAL[3:0] bits are zero. In this case, the input
signal is delayed 3 clock edges of the FTM input clock. If (CHnFVAL[3:0] ≠ 0000), then
the input signal is delayed by the minimum pulse width (CHnFVAL[3:0] × 4 FTM input
clocks) plus a further 4 rising edges of the FTM input clock: two rising edges to the
Functional description
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
920 NXP Semiconductors