NXP Semiconductors Kinetis KE1xZ256, Reference Manual

Page: 376 / 1325

SCG_CSR field descriptions (continued)
Field Description
27–24
SCS
System Clock Source
Returns the currently configured clock source generating the system clock.
0000 Reserved
0001 System OSC (SOSC_CLK)
0010 Slow IRC (SIRC_CLK)
0011 Fast IRC (FIRC_CLK)
0100 Reserved
0101 Low Power FLL (LPFLL_CLK)
0110 Reserved
0111 Reserved
23–20
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
19–16
DIVCORE
Core Clock Divide Ratio
0000 Divide-by-1
0001 Divide-by-2
0010 Divide-by-3
0011 Divide-by-4
0100 Divide-by-5
0101 Divide-by-6
0110 Divide-by-7
0111 Divide-by-8
1000 Divide-by-9
1001 Divide-by-10
1010 Divide-by-11
1011 Divide-by-12
1100 Divide-by-13
1101 Divide-by-14
1110 Divide-by-15
1111 Divide-by-16
15–12
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
11–8
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
7–4
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
DIVSLOW Slow Clock Divide Ratio
0000 Reserved
0001 Divide-by-2
0010 Divide-by-3
0011 Divide-by-4
0100 Divide-by-5
0101 Divide-by-6
0110 Divide-by-7
0111 Divide-by-8
Table continues on the next page...
Memory Map/Register Definition
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
376 NXP Semiconductors