NXP Semiconductors Kinetis KE1xZ256, Reference Manual

Page: 1062 / 1325

42.5.3.1 Prescaler enabled
In Time Counter mode, when the prescaler is enabled, the output of the prescaler directly
clocks the CNR. When the LPTMR is enabled, the CNR will increment every 2
2
to 2
16
prescaler clock cycles. After the LPTMR is enabled, the first increment of the CNR will
take an additional one or two prescaler clock cycles due to synchronization logic.
42.5.3.2 Prescaler bypassed
In Time Counter mode, when the prescaler is bypassed, the selected prescaler clock
increments the CNR on every clock cycle. When the LPTMR is enabled, the first
increment will take an additional one or two prescaler clock cycles due to
synchronization logic.
42.5.3.3 Glitch filter
In Pulse Counter mode, when the glitch filter is enabled, the output of the glitch filter
directly clocks the CNR. When the LPTMR is first enabled, the output of the glitch filter
is asserted, that is, logic 1 for active-high and logic 0 for active-low. The following table
shows the change in glitch filter output with the selected input source.
If Then
The selected input source remains deasserted for at least 2
1
to 2
15
consecutive prescaler clock rising edges
The glitch filter output will also deassert.
The selected input source remains asserted for at least 2
1
to
2
15
consecutive prescaler clock rising-edges
The glitch filter output will also assert.
NOTE
The input is only sampled on the rising clock edge.
The CNR will increment each time the glitch filter output asserts. In Pulse Counter mode,
the maximum rate at which the CNR can increment is once every 2
2
to 2
16
prescaler
clock edges. When first enabled, the glitch filter will wait an additional one or two
prescaler clock edges due to synchronization logic.
Functional description
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
1062 NXP Semiconductors