NXP Semiconductors Kinetis KE1xZ256, Reference Manual

Page: 798 / 1325

NOTE
The sample input must be high for ≥ 2.5 CMP bus clock cycles
to ensure no sampling event is missed.
37.7.7 Windowed/Filtered mode (#7)
This is the most complex mode of operation for the comparator block, as it uses both
windowing and filtering features. It also has the highest latency of any of the modes. This
can be approximated: up to 1 bus clock synchronization in the window fu
[(C0[FILTER_CNT] × C0[FPR]) + 1] × bus clock for the filter function.
When any windowed mode is active, COUTA is clocked by the bus clock whenever
WINDOW = 1. The last latched value is held when WINDOW = 0.
+
-
IRQ
EN, PMODE,HYSCTR[1:0]
INP
INM
FILTER_CNT
INV
COUT
COUT
OPE
SE
CMPO to
PAD
COUTA
0
1
WE
1
0
SE=0
CGMUX
COS
0 1
FILT_PER
bus clock
COS
>
IER/F CFR/F
WINDOW/SAMPLE
Polarity
select
Window
control
Filter
block
Interrupt
control
divided
bus
clock
Clock
prescaler
CMPO
0x01
To other SOC functions
Internal bus
Figure 37-13. Windowed/Filtered mode
The following figure shows the operation timing for this mode, considering uncertainty is
introduced by the internal synchronization for the filter block.
CMP functional modes
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
798 NXP Semiconductors