NXP Semiconductors Kinetis KE1xZ256, Reference Manual

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Write accesses to a locked register are ignored and do not generate a bus error.
43.4.7 Access control
The read access and write access registers are implemented in the chip power domain and
reset on the chip reset. They are not affected by the POR or the software reset. They are
used to block read or write accesses to each register until the next chip system reset.
43.4.8 Interrupt
The RTC interrupt is asserted whenever a status flag and the corresponding interrupt
enable bit are both set. It is always asserted on POR, and software reset. The RTC
interrupt is enabled at the chip level by enabling the chip-specific RTC clock gate control
bit. The RTC interrupt can be used to wakeup the chip from any low-power mode.
The optional RTC seconds interrupt is an edge-sensitive interrupt with a dedicated
interrupt vector that is generated once a second and requires no software overhead (there
is no corresponding status flag to clear). It is enabled in the RTC by the time seconds
interrupt enable bit and enabled at the chip level by setting the chip-specific RTC clock
gate control bit. The frequency of the seconds interrupt defaults to 1 Hz, but can instead
be configured to trigger every 2, 4, 8, 16, 32, 64 or 128 Hz. This interrupt is optional and
may not be implemented on all devices.
43.5 Usage Guide
43.5.1 Clock source information
To get an accuracy clock for RTC, an external 32.768 kHz crystal should be connected to
EXTAL32/XTAL32 pin, or a 32.768 kHz clock signal to RTC_CLKIN pin.
Alternatively, the time counter can be clocked by the LPO 1 kHz and the prescaler will
increment by 32 for each LPO clock, which is not that precisely.
43.5.2 Usage examples
This section shows the application examples of initializing the RTC module, setting the
data time and alarm.
Usage Guide
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
1086 NXP Semiconductors