NXP Semiconductors Kinetis KE1xZ256, Reference Manual

Page: 1045 / 1325

The PWTRDY flag bit indicates that the data can be read in PWTxPPH:L and/or
PWTxNPH:L, whenever there is a valid edge transition happened on the selected
PWTIN.
When PWTRDY bit is set, the updated pulse width register(s) transfers the data to
corresponding 16-bit read buffer(s). The read value of pulse width registers actually
comes from the corresponding read buffers, whenever the chip is in normal run mode or
BDM mode. Reading followed by writing 0 to the PWTRDY flag clears this bit. Until the
PWTRDY bit is cleared, the 16-bit read buffer(s) cannot be updated. But this does not
affect the upload of pulse width registers from the PWT counter.
If another pulse measurement is completed and the pulse width registers are updated, the
clearing of the PWTRDY flag fails, i.e., the PWTRDY will still be set, but the 16-bit read
buffer(s) will be updated again as long as the action is cleared. The user should complete
the pulse width data reading before clearing the PWTRDY flag to avoid missing data.
This mechanism assures that the second pulse measurement will not be lost in case the
MCU does not have enough time to read the first one ready for read. The mechanism is
automatically restarted by an MCU reset , writing 1 to PWTSR bit or writing a 0 to
PWTEN bit followed by writing a 1 to it.
The following figure illustrates the buffering mechanism of pulse width register:
Chapter 41 Pulse Width Timer (PWT)
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
NXP Semiconductors 1045