NXP Semiconductors Kinetis KE1xZ256, Reference Manual

Page: 1018 / 1325

40.4.6 Set Timer Enable Register (LPITx_SETTEN)
This register allows simulataneous enabling of timer channels. Timer channels can be
enabled either by writing '1' to T_EN in respective TCTRLn register or setting the
corresponding bit in this register. Writing a '0' to this register has no effect. CLRTEN
register should be used to disable timer channels simultaneously.
Address: 4003_7000h base + 14h offset = 4003_7014h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
SET_T_EN_3 SET_T_EN_2 SET_T_EN_1 SET_T_EN_0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
LPITx_SETTEN field descriptions
Field Description
31–4
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
3
SET_T_EN_3
Set Timer 3 Enable
Writing '1' to this bit will enable the timer channel 3. This bit can be used in addition to T_EN bit in TCTRL3
register. Writing a 0 will not disable the counter. This bit will be cleared when T_EN bit in TCTRL3 is set to
'0' or '1' is written to the CLR_T_EN_3 bit in CLRTEN register.
0 No effect
1 Enables the Timer Channel 3
2
SET_T_EN_2
Set Timer 2 Enable
Writing '1' to this bit will enable the timer channel 2. This bit can be used in addition to T_EN bit in TCTRL2
register. Writing a 0 will not disable the counter. This bit will be cleared when T_EN bit in TCTRL2 is set to
'0' or '1' is written to the CLR_T_EN_2 bit in CLRTEN register.
0 No Effect
1 Enables the Timer Channel 2
1
SET_T_EN_1
Set Timer 1 Enable
Table continues on the next page...
Memory Map and Registers
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
1018 NXP Semiconductors