NXP Semiconductors Kinetis KE1xZ256, Reference Manual

Page: 65 / 1325

SIM_CHIPCTL field descriptions (continued)
Field Description
19–18
RTC32KCLKSEL
RTC 32K clock input select
00 OSC32 clock output
01 RTC_CLKIN
10 Reserved
11 Reserved
17–16
PWTCLKSEL
PWT clock source select
00 PWT alternative clock is from the TCLK0 pin.
01 PWT alternative clock is from the TCLK1 pin.
10 PWT alternative clock is from the TCLK2 pin.
11 Reserved
15
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
14
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
13
PDB_BB_SEL
PDB back-to-back select
Selects ADC COCO source as pdb back-to-back mode, see Back-to-back acknowledge connectivity in
PDB Inter-connectivity Information for details.
0 PDB0 channel 0 back-to-back operation with ADC0 COCO[1:0] and PDB0 channel 1 back-to-back
operation with ADC1 COCO[1:0]
1 PDB0 Channel 0 back-to-back operation with COCO[0] of ADC0 and COCO[1] of ADC1 ; PDB0
Channel 1 back-to-back operation with COCO[0] of ADC1 and COCO[1] of ADC0
12–11
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
10–8
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
7–6
CLKOUTSEL
CLKOUT Select
Selects the clock to output on the CLKOUT pin.
00 Reseved
01 SCGCLKOUT(SIRC/FIRC/SOSC/LPFLL), see SCG_CLKOUTCNFG register.
10 RTC oscillator (OSC32) clock (32 kHz)
11 LPO clock (128 kHz)
5–4
CLKOUTDIV
CLKOUT divider ratio
00 Divided by 1
01 Divided by 2
10 Divided by 4
11 Divided by 8
3–2
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
ADC_
INTERLEAVE_
EN
ADC interleave channel enable
Select ADC interleave pins. Bit 1 to 0 are for PTB1 and PTB0 respectively.
Table continues on the next page...
Chapter 5 System Integration Module (SIM)
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
NXP Semiconductors 65