NXP Semiconductors Kinetis KE1xZ256, Reference Manual

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detected, that is, the edge selected by channel (n+1) ELSB:ELSA bits. Both DECAP and
channel (n+1) CHF bits indicate when two edges of the pulse were captured and the
C(n)V and C(n+1)V registers are ready for reading.
channel (n) input
(after the filter
DECAPEN bit
C(n+1)V
FTM counter
clear channel (n+1) CHF
problem 1 problem 2
2
1
2
3
channel input)
DECAP bit
set DECAPEN
set DECAP
5
6
7
8
10
3
4 6
5
Note
- The commands set DECAPEN, set DECAP, clear channel (n) CHF, and clear channel (n+1) CHF are made by the user.
4
9
11
12
13
14
9
10
7
8
15
16
17
18
19
20
21
22
23
24
25
26
27
28
15
16
19
20
22 24
- Problem 1: channel (n) input = 1, set DECAP, not clear channel (n) CHF, and clear channel (n+1) CHF.
- Problem 2: channel (n) input = 1, set DECAP, not clear channel (n) CHF, and not clear channel (n+1) CHF.
C(n)V
channel (n+1) CHF bit
channel (n) CHF bit
clear channel (n) CHF
1
Figure 39-88. Dual Edge Capture – One-Shot mode for positive polarity pulse width
measurement
The following figure shows an example of the Dual Edge Capture – Continuous mode
used to measure the positive polarity pulse width. The DECAPEN bit selects the Dual
Edge Capture mode, so it remains set. While the DECAP bit is set the configured
measurements are made. The channel (n) CHF bit is set when the first edge of the
positive polarity pulse is detected, that is, the edge selected by channel (n) ELSB:ELSA
bits. The channel (n+1) CHF bit is set when the second edge of this pulse is detected, that
is, the edge selected by channel (n+1) ELSB:ELSA bits. The channel (n+1) CHF bit
indicates when two edges of the pulse were captured and the C(n)V and C(n+1)V
registers are ready for reading.
Functional description
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
976 NXP Semiconductors