NXP Semiconductors Kinetis KE1xZ256, Reference Manual

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• One channel flag and one sequence error flag per pre-trigger
• DMA support
• Up to 8 pulse outputs (pulse-out's)
• Pulse-out's can be enabled or disabled independently
• Programmable pulse width
NOTE
The number of PDB input and output triggers are chip-specific.
See the chip-specific PDB information for details.
38.2.2 Implementation
In this section, the following letters refer to the number of output triggers:
• N—Total available number of PDB channels.
• n—PDB channel number, valid from 0 to N-1.
• M—Total available pre-trigger per PDB channel.
• m—Pre-trigger number, valid from 0 to M-1.
• Y—Total number of Pulse-Out's.
• y—Pulse-Out number, valid value is from 0 to Y-1.
NOTE
The number of module output triggers to core is chip-specific.
For module to core output triggers implementation, see the chip
configuration information.
38.2.3 Back-to-back acknowledgment connections
PDB back-to-back operation acknowledgment connections are chip-specific. For
implementation, see the chip configuration information.
Chapter 38 Programmable Delay Block (PDB)
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
NXP Semiconductors 825