NXP Semiconductors Kinetis KE1xZ256, Reference Manual

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45.4.5 Peripheral Triggers
The connection of the LPI2C peripheral triggers with other peripherals are device
specific.
45.4.5.1 Master Output Trigger
The LPI2C master generates an output trigger that can be connected to other peripherals
on the device. The master output trigger asserts on both a Repeated START or STOP
condition and remains asserted for one cycle of the LPI2C functional clock divided by the
prescaler.
45.4.5.2 Slave Output Trigger
The LPI2C slave generates an output trigger that can be connected to other peripherals on
the device. The slave output trigger asserts on both a Repeated START or STOP
condition that occurs following a slave address match. It remains asserted until the next
slave SCL pin negation.
45.4.5.3 Input Trigger
The LPI2C input trigger can be selected in place of the LPI2C_HREQ pin to control the
start of a LPI2C master bus transfer. The input trigger must assert for longer than one
LPI2C functional clock cycle to be detected.
45.5 Usage Guide
For master:
• Configure functional clock source by SIM_SOPT2[LPI2C0SRC]
• Reset LPI2C module by LPI2C0_MCR[RST]
• Configure baudrate
• Set Tx/Rx FIFO watermark by LPI2C0_MFCR
• Enable Master mode by set LPI2C0_MCR[MEN]
For slave:
• Configure functional clock source by SIM_SOPT2[LPI2C0SRC]
• Set the slave address into LPI2C0_SAMR
• Configure the TDF only be set in the Slave-Transmit condition by
LPI2C0_SCFGR1[TXCFG]
Chapter 45 Low Power Inter-Integrated Circuit (LPI2C)
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
NXP Semiconductors 1173