NXP Semiconductors Kinetis KE1xZ256, Reference Manual

Page: 1259 / 1325

Table 47-10. I2C Master Configuration (continued)
Register Value Comments
SHIFTBUFn Data to transmit Transmit data can be written to
SHIFTBUFBBS[7:0], use the Shifter
Status Flag to indicate when data can be
written using interrupt or DMA request.
SHIFTBUF(n+1) Data to receive Received data can be read from
SHIFTBUFBIS[7:0], use the Shifter
Status Flag to indicate when data can be
read using interrupt or DMA request.
47.5.6 I2S Master
I2S master mode can be supported using two Timers, two Shifters and four Pins. One
timer is used to generate the bit clock and control the shifters and one timer is used to
generate the frame sync. FlexIO waits for the first write to the transmit data buffer before
enabling bit clock and frame sync generation. Data transfers can be supported using the
DMA controller and the shifter error flag will set on transmit underrun or receive
overflow.
The bit clock frequency is an even integer divide of the FlexIO clock frequency, and the
initial frame sync assertion occurs at the same time as the first bit clock edge. The timer
uses the start bit to ensure the frame sync is generated one clock cycle before the first
output data.
Due to synchronization delays, the setup time for the receiver input is 1.5 FlexIO clock
cycles, so the maximum baud rate is divide by 4 of the FlexIO clock frequency.
Table 47-11. I2S Master Configuration
Register Value Comments
SHIFTCFGn 0x0000_0001 Load transmit data on first shift and stop
bit disabled.
SHIFTCTLn 0x0003_0002 Configure transmit using Timer 0 on
rising edge of clock with output data on
Pin 0.
SHIFTCFG(n+1) 0x0000_0000 Start and stop bit disabled.
SHIFTCTL(n+1) 0x0080_0101 Configure receive using Timer 0 on
falling edge of clock with input data on
Pin 1.
TIMCMPn 0x0000_3F01 Configure 32-bit transfer with baud rate
of divide by 4 of the FlexIO clock. Set
TIMCMP[15:8] = (number of bits x 2) - 1.
Set TIMCMP[7:0] = (baud rate divider /
2) - 1.
Table continues on the next page...
Chapter 47 Flexible I/O (FlexIO)
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
NXP Semiconductors 1259