NXP Semiconductors Kinetis KE1xZ256, Reference Manual

Page: 1118 / 1325

Table 44-4. LPSPI Timing Parameters
Field Description Min Max
SCKDIV Configures the LPSPI_SCK
clock period to (2)
cycles. When configured to an
odd number of cycles, the first
half of the LPSPI_SCK cycle
is one cycle longer than the
second half.
0 (2 cycles) 255 (257 cycles)
DBT Configures the minimum
delay between PCS negation
and the next PCS assertion to
(DBT + 2) cycles. When the
command word is updated
between transfers, there is a
minimum of (DBT/2)+1 cycles
between the command word
update and any change on
LPSPI_PCS pins.
0 (2 cycles) 255 (257 cycles)
DBT Configures the delay during a
continuous transfer between
the last SCK edge of a frame
and the first SCK edge of the
continuing frame to (DBT + 1)
cycles. This is useful where
the external slave requires a
large delay between different
words of a SPI bus transfer.
0 (1 cycle) 255 (256 cycles)
PCSSCK Configures the minimum
delay between PCS assertion
and the first SCK edge to
( 1) cycles.
0 (1 cycle) 255 (256 cycles)
SCKPCS Configures the minimum
delay between the last SCK
edge and the PCS assertion
to ( 1) cycles.
0 (1 cycle) 255 (256 cycles)
44.4.2.4 Pin Configuration
The LPSPI_SIN and LPSPI_SOUT pins can be configured via the PINCFG configuration
to swap directions or even support half-duplex transfers on the same pin.
The OUTCFG configuration can be used to determine if output data pin (eg:
LPSPI_SOUT) will tristate when the LPSPI_PCS is negated, or if it will simply retain the
last value. When configuring for half-duplex transfers using the same data pin in single
bit transfer mode, or any transfer in 2-bit and 4-bit transfer modes, then the output data
pins must be configured to tristate when LPSPI_PCS is negated.
Functional description
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
1118 NXP Semiconductors