NXP Semiconductors Kinetis KE1xZ256, Reference Manual

Page: 1190 / 1325

Field Function
0 - Receive data not inverted.
1 - Receive data inverted.
27
RWUID
Receive Wake Up Idle Detect
For RWU on idle character, RWUID controls whether the idle character that wakes up the receiver sets
the IDLE bit. For address match wakeup, RWUID controls if the IDLE bit is set when the address does
not match. This bit should only be changed when the receiver is disabled.
0 - During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle
character. During address match wakeup, the IDLE bit does not get set when an address does not
match.
1 - During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle
character. During address match wakeup, the IDLE bit does get set when an address does not
match.
26
BRK13
Break Character Generation Length
BRK13 selects a longer transmitted break character length. Detection of a framing error is not affected by
the state of this bit. This bit should only be changed when the transmitter is disabled.
0 - Break character is transmitted with length of 9 to 13 bit times.
1 - Break character is transmitted with length of 12 to 15 bit times.
25
LBKDE
LIN Break Detection Enable
LBKDE selects a longer break character detection length. While LBKDE is set, receive data is not stored
in the receive data buffer.
0 - LIN break detect is disabled, normal break character can be detected.
1 - LIN break detect is enabled. LIN break character is detected at length of 11 bit times (if M = 0)
or 12 (if M = 1) or 13 (M10 = 1).
24
RAF
Receiver Active Flag
RAF is set when the receiver detects the beginning of a valid start bit, and RAF is cleared automatically
when the receiver detects an idle line.
0 - LPUART receiver idle waiting for a start bit.
1 - LPUART receiver active (RXD input not idle).
23
TDRE
Transmit Data Register Empty Flag
When the transmit FIFO is enabled, TDRE will set when the number of datawords in the transmit FIFO
(LPUART_DATA) is equal to or less than the number indicated by LPUART_WATER[TXWATER]). To
clear TDRE, write to the LPUART data register (LPUART_DATA) until the number of words in the
transmit FIFO is greater than the number indicated by LPUART_WATER[TXWATER]. When the transmit
FIFO is disabled,TDRE will set when the transmit data register (LPUART_DATA) is empty. To clear
TDRE, write to the LPUART data register (LPUART_DATA).
TDRE is not affected by a character that is in the process of being transmitted, it is updated at the start of
each transmitted character.
0 - Transmit data buffer full.
1 - Transmit data buffer empty.
22
TC
Transmission Complete Flag
TC is cleared when there is a transmission in progress or when a preamble or break character is loaded.
TC is set when the transmit buffer is empty and no data, preamble, or break character is being
transmitted. When TC is set, the transmit data output signal becomes idle (logic 1). TC is cleared by
writing to LPUART_DATA to transmit new data, queuing a preamble by clearing and then setting
LPUART_CTRL[TE], queuing a break character by writing 1 to LPUART_CTRL[SBK].
0 - Transmitter active (sending data, a preamble, or a break).
1 - Transmitter idle (transmission activity complete).
21
RDRF
Receive Data Register Full Flag
Table continues on the next page...
Register definition
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
1190 NXP Semiconductors