NXP Semiconductors Kinetis KE1xZ256, Reference Manual

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3.3 Core Component Configuration
The processor supports optional tightly-coupled system components. The following table
lists the specific configuration of the Cortex-M0+ core on this device.
Component name Present on this device Note
Single-cycle Multiplier YES
Single-cycle IO Port YES
SysTick YES
Halting debug YES
Watchpoint YES Include 2 comparators
Breakpoint YES Include 2 comparators
MTB YES
WIC YES
Vector Table Offset Support YES
Unprivileged/Privileged Support YES
SWD YES
MPU Not present
3.4 SysTick Clock Configuration
The System Tick Timer's clock source is always the core clock (CORE_CLK) on this
device. This results in the following:
• The CLKSOURCE bit in SysTick Control and Status Register (SYST_CSR) is
always set to select the core clock.
• Because the timing reference (CORE_CLK) is a variable frequency, the TENMS bit
in the SysTick Calibration Value Register (SYST_CALIB) is always zero.
• The NOREF bit in SysTick Calibration Value Register (SYST_CALIB) is always
set, implying that CORE_CLK is the only available source of reference timing.
Chapter 3 Core Overview
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
NXP Semiconductors 55