NXP Semiconductors Kinetis KE1xZ256, Reference Manual

Page: 1058 / 1325

LPTMRx_CSR field descriptions (continued)
Field Description
3
TPP
Timer Pin Polarity
Configures the polarity of the input source in Pulse Counter mode. TPP must be changed only when the
LPTMR is disabled.
0 Pulse Counter input source is active-high, and the CNR will increment on the rising-edge.
1 Pulse Counter input source is active-low, and the CNR will increment on the falling-edge.
2
TFC
Timer Free-Running Counter
When clear, TFC configures the CNR to reset whenever TCF is set. When set, TFC configures the CNR to
reset on overflow. TFC must be altered only when the LPTMR is disabled.
0 CNR is reset whenever TCF is set.
1 CNR is reset on overflow.
1
TMS
Timer Mode Select
Configures the mode of the LPTMR. TMS must be altered only when the LPTMR is disabled.
0 Time Counter mode.
1 Pulse Counter mode.
0
TEN
Timer Enable
When TEN is clear, it resets the LPTMR internal logic, including the CNR and TCF. When TEN is set, the
LPTMR is enabled. While writing 1 to this field, CSR[5:1] must not be altered.
0 LPTMR is disabled and internal logic is reset.
1 LPTMR is enabled.
42.4.2 Low Power Timer Prescale Register (LPTMRx_PSR)
Address: 4004_0000h base + 4h offset = 4004_0004h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
PRESCALE PBYP PCS
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
LPTMRx_PSR field descriptions
Field Description
31–7
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
6–3
PRESCALE
Prescale Value
Table continues on the next page...
Memory map and register definition
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
1058 NXP Semiconductors