NXP Semiconductors Kinetis KE1xZ256, Reference Manual

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SCG_CSR field descriptions (continued)
Field Description
1000 Reserved
1001 Reserved
1010 Reserved
1011 Reserved
1100 Reserved
1101 Reserved
1110 Reserved
1111 Reserved
18.3.4 Run Clock Control Register (SCG_RCCR)
This register controls the system clock source and the system clock dividers for the core,
platform, external and bus clock domains when in Run mode only. This register can only
be written using a 32-bit write. Selecting a different clock source when in RUN requires
that clock source to be enabled first and be valid before system clocks switch to that
clock source. If system clock divide ratios also change when selecting a different clock
mode when in RUN, new system clock divide ratios will not take affect until new clock
source is valid.
Address: 4006_4000h base + 14h offset = 4006_4014h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
SCS
0
DIVCORE Reserved
0 0
DIVSLOW
W
Reset
0 0 0 0 0 0 1 1 0 0 0 0 * * * * 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
* Notes:
DIVCORE field: The reset value is controlled by user FOPT bits that get uploaded during reset. The two valid reset values
are div-by-1 and div-by-2
•
SCG_RCCR field descriptions
Field Description
31–28
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
27–24
SCS
System Clock Source
Selects the clock source generating the system clock in Run mode. Attempting to select a clock that is not
valid will be ignored. Selecting a different clock source when in Run mode requires that clock source to be
enabled first and be valid before system clocks are allowed to switch to that clock source.
0000 Reserved
0001 System OSC (SOSC_CLK)
0010 Slow IRC (SIRC_CLK)
0011 Fast IRC (FIRC_CLK)
Table continues on the next page...
Chapter 18 System Clock Generator (SCG)
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
NXP Semiconductors 377