NXP Semiconductors Kinetis KE1xZ256, Reference Manual

Page: 993 / 1325

To avoid inconsistencies, the field FRACMOD is cleared when
the field MOD of the register MOD is updated with the value of
its write buffer.
The PWM period dithering is not available:
• when the FTM counter is a free running counter,
• when the FTM is in quadrature decoder mode.
39.5.33.1.1 Up Counting
When the FTM counter is an up counter and the PWM period dithering is enabled, at the
end of each PWM period, the FRACMOD value is added to an internal 5-bit
accumulator. When this accumulator overflows (that is, the result of the adding is greater
or equal than 0x20), then one unit of FTM counter is added to the end of the current
PWM period, and the accumulator remains with the rest of the subtraction: (the result of
this adding - 0x20).
Due to one unit of FTM counter that can be added to the PWM period, the largest valid
value for MOD is 0xFFFE for PWM period dithering with unsigned counting and
0x7FFE for PWM period dithering with signed counting.
The figure belows an examples of PWM period dithering when the FTM counter is an up
counter.
Chapter 39 FlexTimer Module (FTM)
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
NXP Semiconductors 993