NXP Semiconductors Kinetis KE1xZ256, Reference Manual

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Chapter 4
Interrupts
4.1 Introduction
The ARM Cortex-M0+ processor includes an interrupt controller called the Nested
Vectored Interrupt Controller (NVIC). It is closely coupled to the processor core to
provide outstanding interrupt handling abilities and low latency interrupt processing. The
NVIC supports nested interrupt, dynamic priority changes, interrupt masking and
interrupt tail-chaining. In addition, the NVIC also supports re-locatable vector table and
an external Nonmaskable Interrupt (NMI).
The NVIC registers are located within the processor's internal System Control Space
(SCS) with base address of 0xE000E000. Most of the NVIC registers are accessible only
in privileged mode. The detailed NVIC functionalities and registers descriptions are
discussed in the following documents from ARM web.
• Cortex-M0+ Devices Generic User Guide
• Cortex-M0+ Technical Reference Manual
4.2 NVIC configuration
The NVIC supports configurable interrupt number and level of priority. The following
sections speficy the exact priority level and interrupt vectors implemented on this device.
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
NXP Semiconductors 57