NXP Semiconductors Kinetis KE1xZ256, Reference Manual

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Channel 0
pre-trigger 0
Channel 1
pre-trigger 0
Channel 0
pre-trigger 1
Channel 1
pre-trigger 1
38.2 Introduction
The Programmable Delay Block (PDB) provides controllable delays from either an
internal or an external trigger, or a programmable interval tick, to the hardware trigger
inputs of ADCs. The PDB can optionally provide pulse outputs (Pulse-Out's) that are
used as the sample window in the CMP block.
38.2.1 Features
• Up to 15 trigger input sources and one software trigger source
• Up to 8 configurable PDB channels for ADC hardware trigger
• One PDB channel is associated with one ADC
• One trigger output for ADC hardware trigger and up to 8 pre-trigger outputs for
ADC trigger select per PDB channel
• Trigger outputs can be enabled or disabled independently
• One 16-bit delay register per pre-trigger output
• Optional bypass of the delay registers of the pre-trigger outputs
• Operation in One-Shot or Continuous modes
• Optional back-to-back mode operation, which enables the ADC conversions
complete to trigger the next PDB channel
• One programmable delay interrupt
• One sequence error interrupt
Introduction
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
824 NXP Semiconductors