NXP Semiconductors Kinetis KE1xZ256, Reference Manual

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SCG_SIRCDIV field descriptions (continued)
Field Description
Clock divider 2 for Slow IRC. Used by modules that need an asynchronous clock source.
000 Output disabled
001 Divide by 1
010 Divide by 2
011 Divide by 4
100 Divide by 8
101 Divide by 16
110 Divide by 32
111 Divide by 64
7–3
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
SIRCDIV1 Slow IRC Clock Divide 1
Clock divider 1 for Slow IRC. Used to generate the clock source for modules that need an asynchronous
clock source.
000 Output disabled
001 Divide by 1
010 Divide by 2
011 Divide by 4
100 Divide by 8
101 Divide by 16
110 Divide by 32
111 Divide by 64
18.3.12 Slow IRC Configuration Register (SCG_SIRCCFG)
The SIRCCFG register cannot be changed when the slow IRC clock is enabled. When the
slow IRC clock is enabled, writes to this register are ignored, and there is no transfer
error.
Address: 4006_4000h base + 208h offset = 4006_4208h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
RANGE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Chapter 18 System Clock Generator (SCG)
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
NXP Semiconductors 389