NXP Semiconductors Kinetis KE1xZ256, Reference Manual

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In this diagram, only one PDB channel n, and one Pulse-Out y are shown. The PDB-
enabled control logic and the sequence error interrupt logic are not shown.
38.2.5 Modes of operation
PDB ADC trigger operates in the following modes:
• Disabled—Counter is off, all pre-trigger and trigger outputs are low if PDB is not in
back-to-back operation of Bypass mode.
• Debug—Counter is paused when processor is in Debug mode.
• Enabled One-Shot—Counter is enabled and restarted at count zero upon receiving a
positive edge on the selected trigger input source or software trigger is selected and
SC[SWTRIG] is written with 1. In each PDB channel, an enabled pre-trigger asserts
once per trigger input event. The trigger output asserts whenever any of the pre-
triggers is asserted.
• Enabled Continuous—Counter is enabled and restarted at count zero. The counter is
rolled over to zero again when the count reaches the value specified in the modulus
register, and the counting is restarted. This enables a continuous stream of pre-
triggers/trigger outputs as a result of a single trigger input event.
• Enabled Bypassed—The pre-trigger and trigger outputs assert immediately after a
positive edge on the selected trigger input source or software trigger is selected and
SC[SWTRIG] is written with 1, that is the delay registers are bypassed. It is possible
to bypass any one or more of the delay registers; therefore, this mode can be used in
conjunction with One-Shot or Continuous mode.
38.3 PDB signal descriptions
This table shows the detailed description of the external signal.
Table 38-4. PDB signal descriptions
Signal Description I/O
EXTRG External Trigger Input Source
If the PDB is enabled and external trigger input source is selected, a
positive edge on the EXTRG signal resets and starts the counter.
I
38.4 Memory map and register definition
Chapter 38 Programmable Delay Block (PDB)
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
NXP Semiconductors 827