4. A configurable up-down counter or a PRBS method for generating “1”; If using up-
down counter, the counter value is limited by TSI_SSC2[MOVE_NOCHARGE_MIN]
and TSI_SSC2[MOVE_NOCHARGE_MAX]; If using PRBS method, the length of the
"1" is controlled by the output of the PRBS method;
5. A configurable up-down counter for “0”, the max value of the counter is controlled by
TSI_SSC0[CHARGE_NUM].
Figure 48-9. Spread spectrum clocking timing
The upper figure is presenting the timing of input system clock and the SSC output bit.
t1: controlled by component 3 and TSI_SSC0[BASE_NOCHARGE_NUM];
t2: controlled by component 4, and TSI_SSC2[MOVE_NOCHARGE_MIN] /
TSI_SSC2[MOVE_NOCHARGE_MAX] if using up-down counter, or by PRBS output
if using PRBS method;
t3: controlled by component 5 and TSI_SSC0[CHARGE_NUM];
So the average frequency of the SSC output bit will be:
.
Functional description
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
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NXP Semiconductors
Summary of Contents for Kinetis KE1xZ256
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