NXP Semiconductors Kinetis KE1xZ256, Reference Manual

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17.4.2 VLPR mode clocking
The clock dividers should not be changed while in VLPR mode. They must be
programmed prior to entering VLPR mode to guarantee:
• the core/system clocks are less than or equal to 4 MHz
• the flash/bus memory clocks is less than or equal to 1 MHz
17.5 Clock Gating
The clock to most of the modules can be individually gated on and off using the PCC
module. After any reset, PCC disables part of the clock to the corresponding module to
conserve power. Prior to initializing a module, set the corresponding clock gating control
bits in PCC register to enable the clock. Before turning off the clock, make sure to disable
the module.
Any bus access to a peripheral that has its bus interface clock disabled (CGC=0 in PCC
module) will generate a bus fault. While any bus access to a peripheral that has its
functional clock disabled (PCS=0 in PCC module) will not return a fault, but the module
cannot work properly.
NOTE
Changes to clock source should be done when clock is gated by
PCC to avoid glitches to output clock.
17.6 Module clocks
The following table summarizes the clocks associated with each module.
Table 17-1. Peripheral Clock Summary
Module Name Bus Interface
Clock Gating
Peripheral Functional Clock Max Frequency of Clock
Source
Gated by [CGC]
bit of PCC
Clocks controlled
by [PCS] bits of
PCC
1
Clocks controlled by
registers inside
module
Communications
LPUART0 – LPUART2 Yes FIRC_CLK,
SIRC_CLK, - Max: 72 MHz
Table continues on the next page...
Clock Gating
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
360 NXP Semiconductors