NXP Semiconductors Kinetis KE1xZ256, Reference Manual

Page: 1015 / 1325

40.4.3 Module Control Register (LPITx_MCR)
Address: 4003_7000h base + 8h offset = 4003_7008h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
DBG_EN
DOZE_EN
SW_
RST
M_CEN
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
LPITx_MCR field descriptions
Field Description
31–4
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
3
DBG_EN
Debug Enable Bit
Allows the timer channels to be stopped when the device enters the Debug mode
0 Timer channels are stopped in Debug mode
1 Timer channels continue to run in Debug mode
2
DOZE_EN
DOZE Mode Enable Bit
Allows the timer channels to be stopped or continue to run when the device enters the DOZE mode
0 Timer channels are stopped in DOZE mode
1 Timer channels continue to run in DOZE mode
1
SW_RST
Software Reset Bit
Resets all channels and registers, except the Module Control Register. Remains set until cleared by
software.
0 Timer channels and registers are not reset
1 Timer channels and registers are reset
0
M_CEN
Module Clock Enable
Enables the peripheral clock to the module timers. M_CEN bit must be asserted when writing to timer
registers. Both clocks (bus clock and peripheral clock) must be enabled, to allow for clock synchronization
and update of register bits.
NOTE: Writing to the MSR, SETTEN , CLRTEN, TCTRL, and TVAL registers while M_CEN = 0, will lead
to the assertion of a transfer error for that bus cycle. Writing to CVAL and reserved registers will
always generate a transfer error.
Table continues on the next page...
Chapter 40 Low-power Periodic Interrupt Timer (LPIT)
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
NXP Semiconductors 1015