NXP Semiconductors Kinetis KE1xZ256, Reference Manual

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21.2.2.6 Stop mode acknowledge error (SACKERR)
This reset is generated if the core attempts to enter stop mode, but not all modules
acknowledge stop mode within 1025 cycles of the LPO clock.
A module might not acknowledge the entry to stop mode if an error condition occurs. The
error can be caused by a failure of an external clock input to a module.
The RCM_SRS[SACKERR] bit is set to indicate this reset source.
21.2.2.7 Software reset (SW)
The SYSRESETREQ bit in the System Control Block's (SCB) application interrupt and
reset control register can be set to force a software reset on the device. (See ARM's
Cortex-M user guide for the full description of the register fields, especially the
VECTKEY field requirements.) Setting SYSRESETREQ generates a software reset
request. This reset forces a system reset of all major components except for the debug
module. A software reset causes the RCM_SRS[SW] bit to set.
21.2.2.8 Lockup reset (LOCKUP)
The LOCKUP gives immediate indication of seriously errant kernel software. This is the
result of the core being locked because of an unrecoverable exception following the
activation of the processor’s built in system state protection hardware.
The LOCKUP condition causes a system reset and also causes the RCM_SRS[LOCKUP]
bit to set.
21.2.2.9 MDM-AP system reset request
Set the system reset request bit in the MDM-AP control register to initiate a system reset.
This is the primary method for resets via the SWD interface. The system reset is held
until this bit is cleared.
Set the core hold reset bit in the MDM-AP control register to hold the core in reset as the
rest of the chip comes out of system reset.
21.2.3 MCU Resets
A variety of resets are generated by the MCU to reset different modules.
Chapter 21 Reset and Boot
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
NXP Semiconductors 463