NXP Semiconductors Kinetis KE1xZ256, Reference Manual

Page: 1056 / 1325

42.3 LPTMR signal descriptions
Table 42-2. LPTMR signal descriptions
Signal I/O Description
LPTMR_ALT n I Pulse Counter Input pin
42.3.1 Detailed signal descriptions
Table 42-3. LPTMR interface—detailed signal descriptions
Signal I/O Description
LPTMR_ALT n I Pulse Counter Input
The LPTMR can select one of the input pins to be used in Pulse Counter mode.
State meaning Assertion—If configured for pulse counter mode with
active-high input, then assertion causes the CNR to
increment.
Deassertion—If configured for pulse counter mode with
active-low input, then deassertion causes the CNR to
increment.
Timing Assertion or deassertion may occur at any time; input may
assert asynchronously to the bus clock.
42.4 Memory map and register definition
NOTE
The LPTMR registers are reset only on a POR or LVD event.
See
LPTMR power and reset for more details.
LPTMR memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4004_0000 Low Power Timer Control Status Register (LPTMR0_CSR) 32 R/W 0000_0000h 42.4.1/1057
4004_0004 Low Power Timer Prescale Register (LPTMR0_PSR) 32 R/W 0000_0000h 42.4.2/1058
4004_0008 Low Power Timer Compare Register (LPTMR0_CMR) 32 R/W 0000_0000h 42.4.3/1060
4004_000C Low Power Timer Counter Register (LPTMR0_CNR) 32 R/W 0000_0000h 42.4.4/1060
LPTMR signal descriptions
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
1056 NXP Semiconductors