NXP Semiconductors Kinetis KE1xZ256, Reference Manual

Page: 1115 / 1325

the FRAMESZ configuration. The command word is then pulled from the FIFO and
controls all subsequent transfers (or until the next update to the command word).
• If the LPSPI is busy and the existing CONT bit is set and the new CONTC value is
set, the command word is pulled from the FIFO during the last LPSPI_SCK pulse of
the existing frame (based on FRAMESZ configuration) and the frame continues
using the new command value for the rest of the frame (or until the next update to the
command word). When CONTC is set, only the lower 24-bits of the command word
are updated.
The current state of the existing command word can be read by reading the transmit
command register. It requires at least three LPSPI functional clock cycles for the transmit
command register to update after it is written (assuming an empty FIFO) and the LPSPI
must be enabled (MCR[MEN] is set).
Writing the transmit command register does not initiate a SPI bus transfer, unless the
TXMSK bit is set. When TXMSK is set, a new command word will not be loaded until
the end of the existing frame (based on FRAMESZ configuration) and the TXMSK bit
will be cleared at the end of the transfer.
The following table describes the attributes that are controlled by the command word.
Table 44-3. LPSPI Command Word
Field Description Modify During Transfer
CPOL Configures polarity of the LPSPI_SCK
pin. Any change of CPOL value will
cause a transition on the LPSPI_SCK
pin.
N
CPHA Configures clock phase of transfer. N
PRESCALE Configures prescaler used to divide the
LPSPI functional clock to generate the
timing parameters of the SPI bus
transfer. Changing PRESCALE in
conjunction with PCS allows the LPSPI
to connect to different slave devices at
different frequencies.
N
PCS Configures which LPSPI_PCS asserts
for the transfer, the polarity of
LPSPI_PCS is static and configured by
PCSPOL. If PCSCFG is set, then
PCS[3:2] should not be selected.
N
LSBF Configures if LSB (bit 0) or MSB (bit 31
for a 32-bit word) is transmitted/received
first.
Y
BYSW Enables byte swap on each 32-bit word
when transmitting and receiving data.
Can be useful when interfacing to
devices that organize data as big
endean.
Y
Table continues on the next page...
Chapter 44 Low Power Serial Peripheral Interface (LPSPI)
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
NXP Semiconductors 1115