NXP Semiconductors Kinetis KE1xZ256, Reference Manual

Page: 119 / 1325

The cycle-by-cycle BME operations are detailed in the following table.
Table 8-5. Cycle definitions of decorated load: load-and-clear 1 bit
Pipeline Stage Cycle
x x+1 x+2
BME AHB_ap Forward addr to memory;
Decode decoration; Capture
address, attributes Recirculate captured addr +
attr to memory as slave_wt <next>
BME AHB_dp <previous> Perform memory read; Form
bit mask; Extract bit from
rdata; Form (rdata & ~mask)
and capture destination data
in register Return extracted bit to master;
Perform write sending
registered data to memory
8.4.2.2 Decorated Load: Load-and-Set 1 Bit (LAS1)
This command loads a 1-bit field defined by the LSB position (b) into the core's general
purpose destination register (Rt) and sets the bit in the memory space after performing an
atomic read-modify-write sequence.
The extracted one bit data field from the memory address is right justified and zero filled
in the operand returned to the core.
The data size is specified by the read operation and can be byte (8-bit), halfword (16-bit)
or word (32-bit).
iolaslb 0 *
0 1
mem_addr
iolaslh 0
0 1
mem_addr
iolaslw 0
0 1 mem_addr
*
*
* *
*
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0
0
0
-
-
b
-
b
b
b
b
b
1
1
1
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
-
-
-
Figure 8-10. Decorated load address: load-and-set 1 bit
where addr[30:29] = 10 for peripheral, addr[28:26] = 011 specifies the load-and-set 1 bit
operation, addr[25:21] is "b", the bit identifier, and mem_addr[19:0] specifies the address
offset into the space based at 0x4000_0000 for peripheral. The "-" indicates an address
bit "don't care".
The decorated Load-and-Set 1 Bit read operation is defined in the following pseudo-code
as:
rdata = iolas1<sz>(accessAddress) // decorated load-and-set 1
tmp = mem[accessAddress & 0xE00FFFFF, size] // memory read
mask = 1 << b // generate bit mask
rdata = (tmp & mask) >> b // read data returned to core
Chapter 8 Bit Manipulation Engine (BME)
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
NXP Semiconductors 119