NXP Semiconductors Kinetis KE1xZ256, Reference Manual

Page: 1080 / 1325

43.3.9 RTC Write Access Register (RTC_WAR)
Address: 4003_D000h base + 800h offset = 4003_D800h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
IERW LRW SRW CRW
TCRW TARW TPRW TSRW
W
Reset 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
RTC_WAR field descriptions
Field Description
31–8
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
7
IERW
Interrupt Enable Register Write
After being cleared, this bit is set only by system reset. It is not affected by software reset.
0 Writes to the Interupt Enable Register are ignored.
1 Writes to the Interrupt Enable Register complete as normal.
6
LRW
Lock Register Write
After being cleared, this bit is set only by system reset. It is not affected by software reset.
0 Writes to the Lock Register are ignored.
1 Writes to the Lock Register complete as normal.
5
SRW
Status Register Write
After being cleared, this bit is set only by system reset. It is not affected by software reset.
0 Writes to the Status Register are ignored.
1 Writes to the Status Register complete as normal.
4
CRW
Control Register Write
After being cleared, this bit is set only by system reset. It is not affected by software reset.
0 Writes to the Control Register are ignored.
1 Writes to the Control Register complete as normal.
3
TCRW
Time Compensation Register Write
After being cleared, this bit is set only by system reset. It is not affected by software reset.
Table continues on the next page...
Register definition
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
1080 NXP Semiconductors