NXP Semiconductors Kinetis KE1xZ256, Reference Manual

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39.5.33.2.1 EPWM Mode
The PWM edge dithering for channel (n) in EPWM mode is enabled when a non-zero
value is written to the channel (n) FRACVAL.
If the channel (n) is in EPWM mode and the PWM edge dithering is enabled, at the end
of each EPWM period, the channel (n) FRACVAL value is added to the channel (n)
internal 5-bit accumulator. When this accumulator overflows (that is, the result of the
adding is greater or equal than 0x20), the accumulator remains with the rest of the
subtraction: (the result of this adding - 0x20).
In this configuration, the initial edge of EPWM duty cycle happens when (FTM counter =
CNTIN), its position is not modified by the PWM edge dithering. If there was not the
overflow of the channel (n) accumulator in the current EPWM period, then the final edge
of EPWM duty cycle happens on the channel (n) match (FTM counter = C(n)V), that is,
its position is not modified by the edge dithering. However, if there was the overflow of
the channel (n) accumulator in the current EPWM period, then the final edge of EPWM
duty cycle happens when (FTM counter = C(n)V + 0x0001).
The figure below shows an example of PWM edge dithering when the channel (n) is in
EPWM mode.
0 1 2 3 4 5 6 7 8 9 A B C 0 1 2 3 4 5 6 7 8 9 A B C
dithering
(one unit of
FTM counter)
channel (n) output
FTM counter
accumulator
0x1B 0x1E
overflow
0x01
0 D C B
A 1
channel (n) is in EPWM with high-true pulses
channel (n) ELSB:ELSA = 2'b10
CNTIN = 0x0000
MOD = 0x000C
C(n)V = 0x0009
channel (n) FRACVAL = 0x03
T is the period of one unit of FTM counter
EPWM duty cycle DC1 =
(C(n)V - CNTIN) x T =
0x0009 x T
EPWM dury cycle DC2 =
(C(n)V - CNTIN + 0x0001) x T =
0x000A x T
Figure 39-107. Channel (n) is in EPWM Mode with PWM Edge Dithering
Assuming:
Chapter 39 FlexTimer Module (FTM)
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
NXP Semiconductors 997