NXP Semiconductors Kinetis KE1xZ256, Reference Manual

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continues until another character that matches MATCH[MA1] is received. If both the
LPUART_BAUD[MAEN1] and LPUART_BAUD[MAEN2] bits are negated, the
receiver operates normally and all data received is transferred to the receive data buffer.
NOTE
Match on, match off operation requires both
LPUART_BAUD[MAEN1] and LPUART_BAUD[MAEN2] to
be asserted.
46.4.3.3 Hardware flow control
To support hardware flow control, the receiver can be programmed to automatically
deassert and assert RTS_B.
• RTS_B remains asserted until the transfer is complete, even if the transmitter is
disabled midway through a data transfer. See Transceiver driver enable using RTS_B
for more details.
• If the receiver request-to-send functionality is enabled, the receiver automatically
deasserts RTS_B if the number of characters in the receiver data register is full or a
start bit is detected that will cause the receiver data register to be full.
• The receiver asserts RTS_B when the number of characters in the receiver data
register is not full and has not detected a start bit that will cause the receiver data
register to be full. It is not affected if STAT[RDRF] is asserted.
• Even if RTS_B is deasserted, the receiver continues to receive characters until the
receiver data buffer is overrun.
• If the receiver request-to-send functionality is disabled, the receiver RTS_B remains
deasserted.
46.4.3.4 Infrared decoder
The infrared decoder converts the received character from the IrDA format to the NRZ
format used by the receiver. It also has a OSR oversampling baud rate clock counter that
filters noise and indicates when a 1 is received.
46.4.3.4.1 Start bit detection
When STAT[RXINV] is cleared, the first falling edge of the received character
corresponds to the start bit. The infrared decoder resets its counter. At this time, the
receiver also begins its start bit detection process. After the start bit is detected, the
Chapter 46 Low Power Universal Asynchronous Receiver/Transmitter (LPUART)
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
NXP Semiconductors 1215