NXP Semiconductors Kinetis KE1xZ256, Reference Manual

Page: 1104 / 1325

LPSPIx_CFGR1 field descriptions (continued)
Field Description
0 Output data retains last value when chip select is negated.
1 Output data is tristated when chip select is negated.
25–24
PINCFG
Pin Configuration
Configures which pins are used for input and output data during single bit transfers.
00 SIN is used for input data and SOUT for output data.
01 SIN is used for both input and output data.
10 SOUT is used for both input and output data.
11 SOUT is used for input data and SIN for output data.
23–19
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
18–16
MATCFG
Match Configuration
Configures the condition that will cause the DMF to set.
000 Match disabled.
001 Reserved
010 Match enabled (1st data word equals MATCH0 OR MATCH1).
011 Match enabled (any data word equals MATCH0 OR MATCH1).
100 Match enabled (1st data word equals MATCH0 AND 2nd data word equals MATCH1).
101 Match enabled (any data word equals MATCH0 AND next data word equals MATCH1)
110 Match enabled (1st data word AND MATCH1 equals MATCH0 AND MATCH1)
111 Match enabled (any data word AND MATCH1 equals MATCH0 AND MATCH1).
15–12
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
11–8
PCSPOL
Peripheral Chip Select Polarity
Configures the polarity of each Peripheral Chip Select pin.
0 The PCSx is active low.
1 The PCSx is active high.
7–4
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
3
NOSTALL
No Stall
In master mode, the LPSPI will stall transfers when the transmit FIFO is empty or receive FIFO is full
ensuring that no transmit FIFO underrun or receive FIFO overrun can occur. Setting this bit will disable
this functionality.
0 Transfers will stall when transmit FIFO is empty or receive FIFO is full.
1 Transfers will not stall, allowing transmit FIFO underrun or receive FIFO overrun to occur.
2
AUTOPCS
Automatic PCS
The LPSPI slave normally requires the PCS to negate between frames for correct operation. Setting this
bit will cause the LPSPI to generate an internal PCS signal at the end of each transfer word when
CPHA=1. When this bit is set, the SCK must remain idle for at least 4 LPSPI functional clock cycles
(divided by PRESCALE configuration) between each word to ensure correct operation. This bit is ignored
in master mode.
Table continues on the next page...
Memory Map and Registers
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
1104 NXP Semiconductors