NXP Semiconductors Kinetis KE1xZ256, Reference Manual

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Table 13-5. Hardware service request process (continued)
Cycle Description
With internal peripheral
bus read and internal
SRAM write
With SRAM read and
internal peripheral bus
write
12 13 This cycle represents the data phase of the last destination
write.
13 14 The eDMA engine completes the execution of the inner minor
loop and prepares to write back the required TCD
n fields into
the local memory. The TCD n word 7 is read and checked for
channel linking or scatter/gather requests.
14 15 The appropriate fields in the first part of the TCD n are written
back into the local memory.
15 16 The fields in the second part of the TCD n are written back into
the local memory. This cycle coincides with the next channel
arbitration cycle start.
16 17 The next channel to be activated performs the read of the first
part of its TCD from the local memory. This is equivalent to
Cycle 4 for the first channel's service request.
Assuming zero wait states on the system bus, DMA requests can be processed every 9
cycles. Assuming an average of the access times associated with internal peripheral bus-
to-SRAM (4 cycles) and SRAM-to-internal peripheral bus (5 cycles), DMA requests can
be processed every 11.5 cycles (4 + (4+5)/2 + 3). This is the time from Cycle 4 to Cycle x
+5. The resulting peak request rate, as a function of the system frequency, is shown in the
following table.
Table 13-6. eDMA peak request rate (MReq/sec)
System frequency (MHz)
Request rate
with zero wait states
Request rate
with wait states
48.0 5.3 4.2
66.6 7.4 5.8
83.3 9.2 7.2
100.0 11.1 8.7
133.3 14.8 11.6
150.0 16.6 13.0
A general formula to compute the peak request rate with overlapping requests is:
PEAKreq = freq / [ entry + (1 + read_ws) + (1 + write_ws) + exit ]
where:
Chapter 13 Enhanced Direct Memory Access (eDMA)
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
NXP Semiconductors 249