NXP Semiconductors Kinetis KE1xZ256, Reference Manual

Page: 204 / 1325

DMA memory map (continued)
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4000_90E4 TCD Signed Source Address Offset (DMA_TCD7_SOFF) 16 R/W Undefined 13.3.23/227
4000_90E6 TCD Transfer Attributes (DMA_TCD7_ATTR) 16 R/W Undefined 13.3.24/228
4000_90E8
TCD Minor Byte Count (Minor Loop Mapping Disabled)
(DMA_TCD7_NBYTES_MLNO)
32 R/W Undefined 13.3.25/229
4000_90E8
TCD Signed Minor Loop Offset (Minor Loop Mapping
Enabled and Offset Disabled)
(DMA_TCD7_NBYTES_MLOFFNO)
32 R/W Undefined 13.3.26/229
4000_90E8
TCD Signed Minor Loop Offset (Minor Loop Mapping and
Offset Enabled) (DMA_TCD7_NBYTES_MLOFFYES)
32 R/W Undefined 13.3.27/231
4000_90EC
TCD Last Source Address Adjustment
(DMA_TCD7_SLAST)
32 R/W Undefined 13.3.28/232
4000_90F0 TCD Destination Address (DMA_TCD7_DADDR) 32 R/W Undefined 13.3.29/232
4000_90F4
TCD Signed Destination Address Offset
(DMA_TCD7_DOFF)
16 R/W Undefined 13.3.30/233
4000_90F6
TCD Current Minor Loop Link, Major Loop Count (Channel
Linking Enabled) (DMA_TCD7_CITER_ELINKYES)
16 R/W Undefined 13.3.31/233
4000_90F6 DMA_TCD7_CITER_ELINKNO 16 R/W Undefined 13.3.32/235
4000_90F8
TCD Last Destination Address Adjustment/Scatter Gather
Address (DMA_TCD7_DLASTSGA)
32 R/W Undefined 13.3.33/236
4000_90FC TCD Control and Status (DMA_TCD7_CSR) 16 R/W Undefined 13.3.34/236
4000_90FE
TCD Beginning Minor Loop Link, Major Loop Count
(Channel Linking Enabled)
(DMA_TCD7_BITER_ELINKYES)
16 R/W Undefined 13.3.35/239
4000_90FE
TCD Beginning Minor Loop Link, Major Loop Count
(Channel Linking Disabled) (DMA_TCD7_BITER_ELINKNO)
16 R/W Undefined 13.3.36/240
13.3.5 Control Register (DMA_CR)
The CR defines the basic operating configuration of the DMA.
Arbitration can be configured to use either a fixed-priority or a round-robin scheme. For
fixed-priority arbitration, the highest priority channel requesting service is selected to
execute. The channel priority registers assign the priorities; see the DCHPRIn registers.
For round-robin arbitration, the channel priorities are ignored and channels are cycled
through (from high to low channel number) without regard to priority.
NOTE
For correct operation, writes to the CR register must be
performed only when the DMA channels are inactive; that is,
when TCDn_CSR[ACTIVE] bits are cleared.
Memory map/register definition
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
204 NXP Semiconductors