NXP Semiconductors Kinetis KE1xZ256, Reference Manual

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Maximum supported baud rate of SPI depends on the clock configuration fields in the
Bootloader Configuration Area (BCA) shown in
Table 22-2 . The typical supported baud
rate is 400 kbps with the factory settings. The actual baud rate is lower or higher than 400
kbps, depending on the actual value of the clockFlags and clockDivider fields in the
BCA.
The SPI peripheral uses the following bus attributes:
• Clock Phase = 1 (Second Edge)
• Clock Polarity = 1 (Active Low)
Because the SPI peripheral in ROM serves as a SPI slave device, each transfer should be
started by the host, and each outgoing packet should be fetched by the host.
The transfer on SPI is slightly different from I2C:
• Host will receive 1 byte after it sends out any byte.
• Received bytes should be ignored when host is sending out bytes to target
• Host starts reading bytes by sending 0x00s to target
• The byte 0x00 will be sent as response to host if target is under the following
conditions:
• Processing incoming packet
• Preparing outgoing data
• Received invalid data
The SPI bus configuration is:
• Phase = 1; data is sampled on rising edges
• Polarity = 1; idle is high
• MSB is transmitted first
For any transfer where the target does not have actual data to send, the target (slave) is
responsible for ensuring that 0x00 bytes will be returned to the host (master). The host
uses framing packets to identify real data and not "dummy" 0x00 bytes (which do not
have framing packets).
The following flowcharts demonstrate how the host reads a ping response, an ACK and a
command response from target via SPI.
Chapter 22 Kinetis ROM Bootloader
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
NXP Semiconductors 521